A micropower analog hearing aid on low voltage CMOS digital process

A two-chip analog micropower hearing aid circuit is developed which is based on a low voltage three micron CMOS process. The novel features of the circuit are the use of adaptive biasing of MOS Translinear Loop (MTL) circuit and an innovative application of an adaptive technique in reducing the value of a degenerating linearising resistor in the input differential stage of the AGC block. The above two measures enable reduction of power consumption and external component count. Class-D amplifier provides high conversion efficiency at the output stage. The proposed configuration is now under integration for developing a one chip general purpose CMOS analog hearing aid with capability to operate with 1.0 volt supply voltage.