Application Specific Small-Scale Reconfigurability

Fixed logic circuit design and fabrication is the preferred implementation route for applications with exacting performance, area, and/or power requirements. However, the resulting fixed logic application-specific integrated circuits (ASICs) lack the flexibility to adapt to faults and other runtime events, to changing design specifications and process parameters, or for multi-function execution. Traditional approaches for achieving hardware flexibility with programmable processors or large-scale, general-purpose reconfigurable fabrics (e.g. field programmable gate arrays (FPGAs)) impose significant area, delay, and power penalties compared to fixed logic ASICs. Small-scale reconfigurability (SSR) is a new design technique that minimizes these penalties by finely integrating into a primarily fixed logic circuit only the amount of reconfigurable logic and interconnect that is required for a particular application, at a gate-level granularity. SSR circuits have the necessary flexibility with ASIC-like efficiency due to the fine integration and application-specific implementation. This dissertation introduces SSR and methodologies for applying SSR to the implementation of flexible systems for three major applications: flexible multi-mode system synthesis, low complexity fine-grained heterogeneous redundancy for online testing and fault tolerance, and yield- and reliability-aware flexible design. Results of applying SSR to these application areas reveal the efficacy of this technique in bridging the efficiency/flexibility gap between traditional fixed logic ASICs and general-purpose reconfigurable fabrics.