A 10b 100MS/s 25.2mW 0.18μm CMOS ADC with various circuit sharing techniques

This work describes a 10b 100MS/s 0.18μm CMOS three-stage pipeline ADC. Two MDACs share an op-amp without MOS switches connected in series while removing a memory effect. Three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC with an active die area of 0.80mm2 shows DNL and INL within 0.58LSB and 0.94LSB, respectively, and consumes 25.2mW at 1.8V and 100MS/s.

[1]  Pedro M. Figueiredo,et al.  Kickback noise reduction techniques for CMOS latched comparators , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Thomas K. Paul,et al.  Wireless LAN Comes of Age: Understanding the IEEE 802.11n Amendment , 2008, IEEE Circuits and Systems Magazine.

[3]  B. Murmann,et al.  A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification , 2009, IEEE Journal of Solid-State Circuits.

[4]  Byung-Geun Lee,et al.  A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-$g_{m}$ Opamp , 2009, IEEE Journal of Solid-State Circuits.

[5]  Minh Son Nguyen,et al.  Design and implementation of flash ADC and DBNS FIR filter , 2009, 2009 International SoC Design Conference (ISOCC).

[6]  K. Bacrania,et al.  A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse , 2007, IEEE Journal of Solid-State Circuits.

[7]  Soon-Kyun Shin,et al.  A fully-differential zero-crossing-based 1.2V 10b 26MS/s pipelined ADC in 65nm CMOS , 2008, 2008 IEEE Symposium on VLSI Circuits.

[8]  G. Geelen,et al.  A fast-settling CMOS op amp for SC circuits with 90-dB DC gain , 1990 .