High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform

We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20 GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.

[1]  Henrik Engseth,et al.  New design of an RSFQ parallel multiply–accumulate unit , 2006 .

[2]  Irina Kataeva,et al.  RSFQ asynchronous serial multiplier and spreading codes generator for multiuser detector , 2003 .

[3]  Nakajima,et al.  Logic design of Josephson network. II , 2002 .

[4]  Nakajima,et al.  Spatiotemporal observation of the soliton-antisoliton collision in a Josephson transmission line. , 1987, Physical review letters.

[5]  I. Shimizu,et al.  Implementation of phase-mode arithmetic elements for parallel signal processing , 2003 .

[6]  Risaburo Sato,et al.  Numerical analysis of vortex motion on Josephson structures , 1974 .

[7]  Y. Horima.  Comparison between an AND Array and a Booth Encoder for Large-Scale Phase-Mode Multipliers , 2003 .

[8]  N. Yoshikawa,et al.  Data-driven self-timed RSFQ high-speed test system , 1997, IEEE Transactions on Applied Superconductivity.

[9]  O. Mukhanov,et al.  Implementation of a FFT radix 2 butterfly using serial RSFQ multiplier-adders , 1995, IEEE Transactions on Applied Superconductivity.

[10]  H. T. Kung,et al.  A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[11]  H. Terai,et al.  A single flux quantum standard logic cell library , 2002 .

[12]  Y. Sawada,et al.  Phase mode Josephson computer system , 1991, IEEE Transactions on Applied Superconductivity.

[13]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[14]  V. Semenov,et al.  RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems , 1991, IEEE Transactions on Applied Superconductivity.

[15]  I. Shimizu,et al.  Improved design for parallel multiplier based on phase-mode logic , 2003 .

[16]  T. Onomi,et al.  Phase-mode pipelined parallel multiplier , 2001 .

[17]  Tsutomu Yamashita,et al.  Mechanical analogue of active Josephson transmission line , 1974 .

[18]  O.A. Mukhanov,et al.  Advanced on-chip test technology for RSFQ circuits , 1997, IEEE Transactions on Applied Superconductivity.

[19]  Jack Sklansky,et al.  Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..

[20]  Louis P. Rubinfield.  A Proof of the Modified Booth's Algorithm for Multiplication , 1975, IEEE Transactions on Computers.

[21]  Nakajima,et al.  Experimental observation of spatiotemporal wave forms of all possible types of soliton-antisoliton interactions in Josephson transmission lines. , 1990, Physical review letters.