Reliability of RDL structured wafer level packages

Wafer level chip scale packaging (WLCSP) is one of the most promising single chip packaging technologies due to advantages of fewer processing steps, lower cost, and enhanced device performance. Moreover, the redistribution layer (RDL) technology is an effective way to improve I/O density of IC packages. However, the reliability of WLP devices with RDL structure is greatly challenged as the pitch size going down. The RDL structure may affect the thermomechanical performance of the solder joints or silicon chips, thus causing unexpected failure. In this paper, RDL structured WLCSPs with pitch size of 500 μm were fabricated. The components with a size of 6×6 mm2 were flip-chip bonded on FR-4 boards. Board level reliabilities of the WLCSP were evaluated by thermal shock test according to JEDEC standard. Furthermore, failure analysis was carried out to find out the failure mechanism and the failure related to the RDL structure was observed. The effect of RDL structure on the reliability of WLP was analyzed with the finite element simulations.

[1]  J. Shah,et al.  C4NP technology: Manufacturability, yields and reliability , 2008, 2008 58th Electronic Components and Technology Conference.

[2]  S. Chen,et al.  A study of board level reliability test with bump structure of WLCSP lead-free solder joints , 2007, 2007 International Microsystems, Packaging, Assembly and Circuits Technology.

[3]  S. Wiese,et al.  Fatigue Life Prediction and Analysis of Wafer Level Packages with SnAgCu Solder Balls , 2006, 2006 1st Electronic Systemintegration Technology Conference.

[4]  Tiao Zhou,et al.  Board level temperature cycling study of large array Wafer Level Package , 2009, 2009 59th Electronic Components and Technology Conference.

[5]  Xuejun Fan,et al.  Design and Reliability in Wafer Level Packaging , 2008, 2008 10th Electronics Packaging Technology Conference.

[6]  U. Sharma,et al.  Reliability comparison of aluminum redistribution based WLCSP designs , 2009, European Microelectronics and Packaging Conference.

[7]  D. Pinjala,et al.  Parametric design and solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP) , 2005, 2005 7th Electronic Packaging Technology Conference.

[8]  E. Beyne,et al.  Improved thermal fatigue reliability for flip chip assemblies using redistribution techniques , 2000, ECTC 2000.