2 V/100 ns 1 T/1 C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and non-relaxation reference cell

Recently, a nonvolatile memory embedded in microcontrollers has been required to have 100 ns access time at 2.0 V for mobile information terminals operating with a re-chargeable battery. To achieve this, this paper proposes new architecture for a ferroelectric nonvolatile memory (FeRAM) comprised of (a) Bitline-Driven Read Scheme and (b) Non-Relaxation Reference Cell for high speed and low voltage operation respectively. Using this architecture, a FeRAM with one transistor and one capacitor per bit (1T/1C) cell can have a performance of 100 ns access time at 2.0 V.

[1]  C. Paz de Araujo,et al.  A 256 kb nonvolatile ferroelectric memory at 3 V and 100 ns , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[2]  T. Sumi.  A 256kb nonvolatile ferroelectric memory at 3V and 100ns , 1994 .

[3]  M. Fukuma,et al.  A 60 ns 1 Mb nonvolatile ferroelectric memory with non-driven cell plate line write/read scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[4]  Toshiyuki Honda,et al.  2 V/12O ns Embedded Flash EEPROM Circuit Technology (Special Issue on ULSI Memory Technology) , 1996 .