A gain boosted fully concurrent dual-band interstage matched LNA operating in 900 MHz/2.4 GHz with sub-2dB Noise Figure

This paper features the design and detailed analysis of a fully concurrent dual-band Low Noise Amplifier (LNA) operating in the GSM 0.9GHz & BLUETOOTH 2.4GHz communication standards having an inter-stage matching inductor. An interstage inductor between the common source stage and the common gate stage is used to increase power gain. In this work, all the circuit components are considered on-chip. The results show that the proposed topology increases the overall gain. The concurrent LNA is designed and simulated in CADENCE using 130nm UMC technology. The current design is especially suitable for use in multi-standard wireless receiver frontends. Simulation results indicate a Noise Figure below 4dB and S21 above 14 dB in all frequency bands while drawing 10mA current from a 1.2V power supply.

[1]  S. Wong,et al.  Physical modeling of spiral inductors on silicon , 2000 .

[2]  T.H. Lee,et al.  A 1.5 V, 1.5 GHz CMOS low noise amplifier , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[3]  H. Hashemi,et al.  Concurrent dual-band CMOS low noise amplifiers and receiver architectures , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[4]  C. Patrick Yue,et al.  Design strategy of on-chip inductors for highly integrated RF systems , 1999, DAC '99.

[5]  Hossein Hashemi,et al.  Concurrent multiband low-noise amplifiers-theory, design, and applications , 2002 .

[6]  S. Lindfors,et al.  0.35 μm CMOS T/R Switch for 2.4 GHz Short Range Wireless Applications , 2004 .

[7]  Ashudeb Dutta,et al.  PSO-based output matching network for concurrent dual-band LNA , 2010, 2010 International Conference on Microwave and Millimeter Wave Technology.