Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories

We present two memory test algorithms for neighborhood pattern sensitive faults (NPSFs), including static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF (ANPSF). March algorithms are widely used in memory testing because of their linear time complexity and ease in built-in self-test (BIST) implementation. Although conventional March algorithms do not generate all neighborhood patterns for testing the NPSFs, they can be modified by using multiple data backgrounds such that all neighborhood patterns can be generated. The proposed multi-background March algorithms have shorter test length than previously proposed ones (68N for detecting SNPSFs and PNPSFs and 96N for detecting all NPSFs). Also, based on the proposed algorithms, linear-time BIST circuit can be implemented with low area overhead.

[1]  Cheng-Wen Wu,et al.  Error catch and analysis for semiconductor memories using March tests , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[2]  Cheng-Wen Wu,et al.  Simulation-based test algorithm generation for random access memories , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[3]  Bruce F. Cockburn.  Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs , 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.

[4]  Paolo Prinetto,et al.  Industrial BIST of embedded RAMs , 1995, IEEE Design & Test of Computers.

[5]  Cheng-Wen Wu.  Testing Embedded Memories: Is BIST The Ultimate Solution? , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

[6]  Ming-Chang Tsai,et al.  BRAINS: a BIST compiler for embedded memories , 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[7]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[8]  Vyacheslav N. Yarmolik,et al.  March PS(23N) test for DRAM pattern-sensitive faults , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

[9]  John P. Hayes,et al.  Detection oF Pattern-Sensitive Faults in Random-Access Memories , 1975, IEEE Transactions on Computers.

[10]  Cheng-Wen Wu,et al.  Cost and benefit models for logic and memory BIST , 2000, DATE '00.

[11]  Elizabeth M. Rudnick,et al.  Diagnostic testing of embedded memories using BIST , 2000, DATE '00.

[12]  Cheng-Wen Wu,et al.  A Programmable BIST Core for Embedded DRAM , 1999, IEEE Des. Test Comput..

[13]  Cheng-Wen Wu,et al.  RAMSES: a fast memory fault simulator , 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

[14]  John P. Hayes.  Testing Memories for Single-Cell Pattern-Sensitive Faults , 1980, IEEE Transactions on Computers.

[15]  Sudhakar M. Reddy,et al.  Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories , 1980, IEEE Transactions on Computers.

[16]  Kozo Kinoshita,et al.  Test Pattern Generation for API Faults in RAM , 1985, IEEE Transactions on Computers.

[17]  Kewal K. Saluja,et al.  Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..