Sequential Design Using SystemVerilog

As most of us know that the sequential design which is edge sensitive and in such kind of the design an output is function of the present inputs and past outputs. The chapter discusses about the important sequential design examples using SystemVerilog. Even the chapter discusses about the procedural blocks such as always_latch and always_ff and their use to design the efficient sequential logic. The chapter covers the SystemVerilog description of various kinds of counters, shift registers and the clocked arithmetic and logic unit.