A hardware accelerator for hierarchical VLSI routing
暂无分享,去创建一个
[1] Masayoshi Tachibana,et al. A Hardware Maze Router with Application to Interactive Rip-Up and Reroute , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Viktor K. Prasanna,et al. An efficient VLSI architecture with applications to geometric problems , 1989, Parallel Comput..
[3] C. P. Ravikumar,et al. Parallel placement on reduced array architecture , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[4] Man-Tak Shing,et al. A decomposition algorithm for circuit routing , 1985 .
[5] R. Nair,et al. Wire-routing machines—New tools for VLSI physical design , 1983, Proceedings of the IEEE.
[6] Tom Blank,et al. A Survey of Hardware Accelerators Used in Computer-Aided Design , 1984, IEEE Design & Test of Computers.
[7] Kai Hwang,et al. Computer architecture and parallel processing , 1984, McGraw-Hill Series in computer organization and architecture.
[8] Alfred V. Aho,et al. The Design and Analysis of Computer Algorithms , 1974 .
[9] C. P. Ravikumar,et al. Parallel circuit partitioning on a reduced array architecture , 1989 .
[10] M. Hanan,et al. On Steiner’s Problem with Rectilinear Distance , 1966 .