A hardware accelerator for hierarchical VLSI routing

Abstract Wire routing is a cpu-bound task in the physical design of VLSI circuits. In the recent past, there has been a widespread interest in speeding up routing algorithms through the use of parallel processing techniques. In this paper we are concerned with the hardware acceleration of a hierarchical routing algorithm, known as the cut-and-paste routing algorithm. This approach for routing is relatively new, and is based on the powerful divide-and-conquer strategy. The area of the chip is recursively divided into smaller and smaller regions, until the routing problem within a region can be handled by a simple optimal router. Then the adjacent regions are successively pasted together to obtain the routing of the entire chip. We identify the inherent parallelism in the algorithm, and show that a parallel router based on the reduced array architecture can be developed for its efficient execution. The advantages of using the reduced array include a reduction in processor count, improved processor utilization, and ease of VLSI implementation.