Sensitivity Analysis of Layout Parasitics, Operating Conditions and Topology Variance on Analog Circuits

In this paper, we investigate the impact of circuit sizing, biasing condition, parasitics effects, topology variance and technology scaling on the performance of analog circuits. Two different dynamic comparator topologies namely Lewis-Gray comparator and Differential-Pair comparator are considered as test cases and their performance is analyzed with two different CMOS technologies namely TSMC cmosp18 and TSMC 90nm technology. The result is used to draw conclusion about the governing influences and emphasize the importance of analog circuit synthesis and automation.