Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver
暂无分享,去创建一个
Qin Tang | Amir Zjajo | Michel Berkelaar | N. P. van der Meijs | Javier Rodríguez | M. Berkelaar | A. Zjajo | Qin Tang | N. V. D. Meijs | Javier Rodríguez | Michel Berkelaar
[1] Bao Liu. Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).
[2] Giorgio Biagetti,et al. Piecewise linear second moment statistical simulation of ICs affected by non‐linear statistical effects , 2010, Int. J. Circuit Theory Appl..
[3] Giorgio Biagetti,et al. Piecewise linear second moment statistical simulation of ICs affected by non-linear statistical effects , 2010 .
[4] Noel Menezes,et al. A multi-port current source model for multiple-input switching effects in CMOS library cells , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[5] A. Gattiker,et al. Timing yield estimation from static timing analysis , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.
[6] Anirudh Devgan. Accurate device modeling techniques for efficient timing simulation of integrated circuits , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.
[7] Erkki Oja,et al. Independent component analysis: algorithms and applications , 2000, Neural Networks.
[8] Martin D. F. Wong,et al. A fast and accurate technique to optimize characterization tables for logic synthesis , 1997, DAC.
[9] Shahin Nazarian,et al. Statistical logic cell delay analysis using a current-based model , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[10] Amir Zjajo,et al. Statistical delay calculation with Multiple Input Simultaneous Switching , 2011, 2011 IEEE International Conference on IC Design & Technology.
[11] Mohab Anis,et al. On statistical timing analysis with inter- and intra-die variations , 2005, Design, Automation and Test in Europe.
[12] K. Ravindran,et al. First-Order Incremental Block-Based Statistical Timing Analysis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] Jianwen Zhu,et al. Transistor-level static timing analysis by piecewise quadratic waveform matching , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[14] Noel Menezes,et al. A nonlinear cell macromodel for digital applications , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[15] Jinjun Xiong,et al. Path criticality computation in parameterized statistical timing analysis , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).
[16] Qin Tang,et al. RDE-based transistor-level gate simulation for statistical static timing analysis , 2010, Design Automation Conference.
[17] Malgorzata Marek-Sadowska,et al. Statistical static timing analysis flow for transistor level macros in a microprocessor , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).
[18] Sarma B. K. Vrudhula,et al. Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[19] Sarma B. K. Vrudhula,et al. Statistical waveform and current source based standard cell models for accurate timing analysis , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[20] Rajendran Panda,et al. Statistical delay computation considering spatial correlations , 2003, ASP-DAC '03.
[21] Qin Tang,et al. Direct Statistical Simulation of Timing Properties in Sequential Circuits , 2012, PATMOS.
[22] Lin Xie,et al. Bound-Based Statistically-Critical Path Extraction Under Process Variations , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[23] P. Peebles. Probability, Random Variables and Random Signal Principles , 1993 .
[24] Rung-Bin Lin,et al. A new statistical approach to timing analysis of VLSI circuits , 1998, Proceedings Eleventh International Conference on VLSI Design.
[25] Masahiro Fukui,et al. Accuracy of the criticality probabilty of a path in statistical timing analysis , 2009, 2009 European Conference on Circuit Theory and Design.
[26] Noel Menezes,et al. A “true” electrical cell model for timing, noise, and power grid verification , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[27] Roberto Manduchi,et al. Independent component analysis of textures , 1999, Proceedings of the Seventh IEEE International Conference on Computer Vision.
[28] Qin Tang,et al. Transistor-Level Waveform Evaluation for Timing Analysis , 2010 .
[29] Murat R. Becer,et al. Transistor level gate modeling for accurate and fast timing, noise, and power analysis , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[30] Carl Sechen,et al. WTA - Waveform-based Timing Analysis for deep submicron circuits , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..
[31] Peivand F. Tehrani,et al. Deep sub-micron static timing analysis in presence of crosstalk , 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).
[32] Huawei Li,et al. Graph partition based path selection for testing of small delay defects , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).
[33] Hakan Yalcin,et al. Transistor-level timing analysis using embedded simulation , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[34] Massoud Pedram,et al. A Current Source Model for CMOS Logic Cells Considering Multiple Input Switching and Stack Effect , 2008, 2008 Design, Automation and Test in Europe.
[35] Angelo Brambilla,et al. Recasting modified nodal analysis to improve reliability in numerical circuit Simulation , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.
[36] A.B. Kahng,et al. Statistical Gate Level Simulation via Voltage Controlled Current Source Models , 2006, 2006 IEEE International Behavioral Modeling and Simulation Workshop.
[37] Martin D. F. Wong,et al. Blade and razor: cell and interconnect delay analysis using current-based models , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[38] Sarvesh Bhardwaj,et al. A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[39] Farid N. Najm,et al. Circuit Simulation: Najm/Circuit Simulation , 2010 .
[40] Lawrence T. Pileggi,et al. Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[41] Qin Tang,et al. Transistor-level gate model based statistical timing analysis considering correlations , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[42] Lawrence T. Pileggi,et al. TETA: transistor-level waveform evaluation for timing analysis , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[43] Farid N. Najm,et al. Circuit Simulation , 2010 .
[44] N. P. van der Meijs,et al. Fast statistical analysis of RC nets subject to manufacturing variabilities , 2011, 2011 Design, Automation & Test in Europe.
[45] Zhuo Feng,et al. Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[46] Yehea I. Ismail,et al. Statistical static timing analysis: how simple can we get? , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[47] T. T. Soong,et al. Random differential equations in science and engineering , 1974 .
[48] Jinjun Xiong,et al. Statistical Path Selection for At-Speed Test , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[49] X. Y. Zheng. Implementing and evaluating a simplified transistor model for timing analysis of integrated circuits , 2012 .