论文信息 - FPGA Implementation of Digital Chaotic Cryptography

FPGA Implementation of Digital Chaotic Cryptography

In this paper, we present the digital chaotic cryptography implementation on FPGA. The system realization uses AR filter and modulo function as a non - linear component. The hardware implementation of FPGA-based which consumed 288 CLBs has been successfully developed for 24 bits fixed point system using 4-th order filter. The maximum clock frequency used in the experiment is 6.747 MHz.

Dewi Utami | Hadi Suwastio | Bambang Sumadjudin

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