2RW dual-port SRAM design challenges in advanced technology nodes

We examine appropriate bitcell layouts for two read/write (2RW) 8T dual-port (DP) SRAM in advanced planar/FinFET technologies. 256-kbit 2RW DP SRAM macros with highly symmetrical 8T DP bitcell were designed and fabricated using 16 nm FinFET technology. The read/write assist with wordline overdrive reduces Vmln by 120 mV, achieving successful operation at below 0.5 V.

[1]  Kevin Zhang,et al.  A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry , 2012, 2012 IEEE International Solid-State Circuits Conference.

[2]  Hidehiro Fujiwara,et al.  A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues , 2010, IEEE Journal of Solid-State Circuits.

[3]  Shien-Yang Wu,et al.  A 16nm FinFET CMOS technology for mobile SoC and computing applications , 2013 .

[4]  Koji Nii,et al.  A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

[5]  Koji Nii,et al.  16 nm FinFET High-k/Metal-gate 256-kbit 6T SRAM macros with wordline overdriven assist , 2014, 2014 IEEE International Electron Devices Meeting.

[6]  T. Iwasaki,et al.  A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment , 2008, 2008 IEEE Symposium on VLSI Circuits.

[7]  Nii Koji,et al.  40nm ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU , 2014 .

[8]  Koji Nii,et al.  Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[9]  Hidehiro Fujiwara,et al.  A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs , 2012, 2012 IEEE International Solid-State Circuits Conference.

[10]  Min Cao,et al.  A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[11]  K. Ishibashi,et al.  A 65 nm Ultra-High-Density Dual-Port SRAM with 0.71um/sup ~/ 8T-Cell for SoC , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..