A Novel High-Speed Parallel Scheme for Data Sorting Algorithm Based on FPGA

Efficient data sorting is important for searching and optimization algorithms in high time demanding fields such as image and multi-media data processing. To accelerate the data sorting algorithm applied in practical normalized crosscorrelation image matching, a novel high-speed parallel sorting scheme based on field programmable gate array (FPGA) is proposed in this paper. When the FPGA chip used has low available logic resource for sorting, the scheme is further extended with random access memory (RAM) as indicators for sorted data to sort large data set. Function and timing simulation with Quartus II 8.0 and practical experiment of the parallel sorting scheme based on the FPGA chip applied in normalized cross-correlation image matching sub-system have shown that this scheme can effectively improve the speed performance with more logic resources usage. Keywords-data sorting algorithm; FPGA; parallel sorting; normalized cross-correlation image matching