Flexible hardware architecture for AES cryptography algorithm

In the numeric communication, much devoted efforts are dedicated to improve security and safety of numeric transactions. Hardware implementation of cryptography algorithm, as the AES, is a good solution to preserve confidentiality and accessibility to the information. In this context, this paper proposes an optimal hardware implementation of AES algorithm. Taking advantages of dynamic partially reconfigurable of FPGA. Implementation result of the proposed architecture shows the interest of this new approach, and confirms the contribution of the reconfigurable FPGA for robust and optimal implementation

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