Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits

In ultra-low-power applications with long standby periods, power-gating technique can be combined with sub-threshold operation to minimize energy. However, in nanometer technologies, we show in this paper that the introduction of the sleep transistor threatens subthreshold circuit robustness because of noise margin degradation. An increase in Vdd to maintain robustness limits the achievable sleep-mode leakage power reduction to 100× with up to 60% active-mode energy penalty. We therefore propose a framework to engineer the sleep transistor under robustness constraint, which shows that a std-Vt long-channel MOSFET is the optimum sleep transistor with 170× leakage reduction at only 20% energy penalty.