Robust Design of CNFET Based Buffered Delay Model and Microwave Pulse Generator

This paper proposes an efficient and robust design of a CNFET based buffered delay circuit. The proposed circuit overcomes several issues of the traditional delay insertion circuits such as low- resolution, device-mismatch and so on. This work also designs a microwave pulse generator circuit using the proposed buffered delay circuit. Microwave pulses of pulse width 9.7 ps can be produced by the pulse generator presented in this paper. Further, variability of delay produced by proposed circuit has been analyzed to prove the immunity against process, voltage and temperature variations. CNFET based circuit proves to be more efficient as compared to its CMOS counterpart in terms of delay variability. The proposed buffered delay circuit also minimizes the effect of rise and fall time of the input signal. The proposed design of buffered delay circuit has been modeled using predictive technology model (PTM) @ 16-nm technology node and verified by simulation results on SPICE.

[1]  Chi-Chou Kao,et al.  Clock skew minimization with adjustable delay buffers restriction , 2013, 2013 International Symposium on Next-Generation Electronics.

[2]  K. Banerjee,et al.  A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies , 2004 .

[3]  Nihar R. Mahapatra,et al.  Comparison and analysis of delay elements , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[4]  K. Roy,et al.  A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies , 2004, ICCAD 2004.

[5]  Frank Vahid,et al.  Using a victim buffer in an application-specific memory hierarchy , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[6]  R. Witte,et al.  Impact of Microwave Pulses on Thermoacoustic Imaging Applications , 2012, IEEE Antennas and Wireless Propagation Letters.

[7]  J. Meindl,et al.  Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI) , 2005, IEEE Electron Device Letters.

[8]  Charles J. Alpert,et al.  Buffer insertion for noise and delay optimization , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  D. Salameh,et al.  Novel Wide Bandwidth GAAS Sampling MMIC using Microstrip Based Nonlinear Transmission Line (NLTL) and NLTL Shock Wave Generator Design , 1998, 1998 28th European Microwave Conference.

[10]  Kaushik Roy,et al.  Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Shih-Hsu Huang,et al.  Clock Period Minimization with Minimum Delay Insertion , 2007, 2007 44th ACM/IEEE Design Automation Conference.