A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications

A novel sub-5-nm node folded cascode structure using dual workfunction (WF) scheme was proposed using fully-calibrated TCAD. Feasible process flows of the cascode device were adopted from those of nanosheet FETs (NSFETs) and complementary FETs. Key process flows were depositing two different separate spacers and etching one spacer selectively, depositing oxide layer in between source/drain epitaxial growths for electrical isolation, and fill-CMP-etch back sequence for dual-WF. The folded cascode device consists of two or three FETs in series, designated as 2-CAS or 3-CAS respectively, under the same active area. Conventional three-stacked NSFETs have larger transconductance (<inline-formula> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula>) than 2-CAS and 3-CAS, but the cascode devices have much larger output resistance (<inline-formula> <tex-math notation="LaTeX">$R_{o}$ </tex-math></inline-formula>) by dual-WF scheme and thus achieve larger intrinsic gain (<inline-formula> <tex-math notation="LaTeX">$A_{V} = G_{m}R_{o}$ </tex-math></inline-formula>). Smaller <inline-formula> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> and larger gate capacitance for the cascode devices decrease the cutoff frequency. But smaller gate-to-drain capacitance by shrunk drain epi along with large <inline-formula> <tex-math notation="LaTeX">$R_{o}$ </tex-math></inline-formula> increases the maximum frequency (<inline-formula> <tex-math notation="LaTeX">$F_{max}$ </tex-math></inline-formula>). Especially, 2-CAS has larger <inline-formula> <tex-math notation="LaTeX">$A_{V}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$F_{max}$ </tex-math></inline-formula> than conventional NSFETs for all the NS widths of 20, 30, and 40 nm and at all the operation voltages of 0.6, 0.7, and 0.8 V, promising for low power mobile applications.

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