Using Boolean satisfiability for computing soft error rates in early design stages

Abstract Soft errors, due to cosmic radiations, are one of the major reliability barriers for VLSI designs. The vulnerability of such systems to soft errors grows exponentially with technology scaling. To meet reliability constraints in a cost-effective way, it is critical to assess soft error reliability parameters in early design stages in order to optimize reliability in the entire design cycle. Unlike soft error modeling for gate-level netlists, soft error propagation models for high-level behavioral designs are not straightforward. In this paper, we present a framework to accurately obtain Soft Error Rate (SER) for high-level (behavioral) descriptions (Verilog or VHDL) in early design stages. We transform the SER problem into equivalent Boolean satisfiability problem and use state-of-the-art SAT-solvers to obtain SER. We have developed an automated flow to convert high-level hardware descriptions into SAT formulations for exact SER computation. We compare our technique to traditional fault simulation techniques for both combinational and sequential circuits. Experiments are carried out on several benchmarks and results are presented. The experimental results show that fault simulations with orders of magnitude run time overhead still result in significantly inaccurate under-estimation of SER values. Unlike fault simulation methods, the presented technique scales well for very large designs.