Single-Wail Haridshake Circuits

Single-rail handshake circuits are introduced as a costeffective implementation of asynchronous circuits. Compared to double-rail implementations, the circuits are smaller, faster, and mre energy-eflcient. Furthermore, in contrast to common belid, all four phases of the fourphase handxhake protocol can be productive. An important selling point for single-rail circuits is that they can be implemented in any (generic) standard-cell library. This facilitates technology migration and makes asynchronous circuits a potential technology of choice for low-power applications. 1 Introdluction Handshake circuits form the intermediate representation in the fully automatic compilation of Tangram programs to Vl,SI circuits [14]. VLSI programs written in Tangram are translated in a transparent way into handshake circuits, which are subsequently, on a componentby-component basis, replaced by gate netlists. The datapaths of these circuits have previously been implemented using double-rail data encoding. With this approach a number of interesting circuits have been realized, such as the chips folr the error decoder of the Digital Compact Cassette plqyer [15]. Double-rail implementations of handshake circuits are robust, but they have two important disadvantages. First of all the readizations are rather area inefficient. Since for each bit two wires are used in the encoding, compared to one wire for synchronous circuits, the area of a double-rail circuit is about twice that of an equivalent synchronous realization. (Each wire has to be driven by some cell, and hence implies transistors and circuit area.) Secondly, double-rail combinational logic is generally implemented using dedicated double-rail cells, not normally available in a standard-cell library. The goal set for the work described in this paper was to reduce the area overhead of handshake circuits and, simultaneously, to map them onto a generic standard-cell library. Both points are essential when striving for acceptance, application, and production of asynchronous circuits on a larger scale. We want to leave handshake circuits as they are, so the compilation from Tangram to handshake circuits should be independent of the style of implementation. We furthermore stick to the standard-cell layout style, four-phase

[1]  Severo M. Ornstein,et al.  Logical design of macromodules , 1967, AFIPS '67 (Spring).

[2]  Erik Brunvand Translating concurrent communicating programs into asynchronous circuits , 1992 .

[3]  David Hung-Chang Du,et al.  Path sensitization in critical path problem , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[4]  Nigel Charles Paver,et al.  The Design and Implementation of an Asynchronous Microprocessor , 1994 .

[5]  Bruce Gilchrist,et al.  Fast Carry Logic for Digital Computers , 1955, IRE Trans. Electron. Comput..

[6]  Kees van Berkel,et al.  Handshake Circuits: An Asynchronous Architecture for VLSI Programming , 1993 .

[7]  Marly Roncken,et al.  Partial scan test for asynchronous circuits illustrated on a DCC error corrector , 1994, Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems.