A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS

This paper presents a 2b/cycle hybrid successive­approximation-register (SAR) analog-to-digital-converter (ADC) architecture with only 1 differential capacitor-DAC (CDAC). Unlike prior multi-bit/cycle SAR works that make use of only the DAC differential mode (DM) voltage, the proposed architecture exploits both the DM and the common mode (CM). By using two degrees of freedom, the proposed ADC can generate 3 comparison levels needed for 2b/cycle without requiring extra DAC arrays. Eliminating extra DAC arrays reduces hardware cost, area, and power. The proposed SAR ADC takes advantage of 1b/cycle conversion mode and sufficient redundancy to address problems of multi-bit/cycle conversions, such as unmatched comparator offsets, kickback noise, and comparator input CM voltage variation. Reconfiguration to 1b/cycle is easily done by disabling the unneeded comparators for 1b/cycle conversion. A 10b prototype ADC is fabricated in 40nm LP CMOS process. It achieves peak 8.5b ENOB at sampling frequency of 300MS/s and consumes 2.1mW, leading to a FoM of 19.3fJ/conv-step.

[1]  Rui Paulo Martins,et al.  26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[2]  Yuan-Ching Lien,et al.  A 4.5-mW 8-b 750-MS/s 2-b/step asynchronous subranged SAR ADC in 28-nm CMOS technology , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[3]  Nan Sun,et al.  A 1.4mW 8b 350MS/s loop-unrolled SAR ADC with background offset calibration in 40nm CMOS , 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

[4]  Patrick Chiang,et al.  Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS , 2010, IEEE Custom Integrated Circuits Conference 2010.

[5]  Franco Maloberti,et al.  A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS , 2011, 2011 IEEE International Solid-State Circuits Conference.

[6]  Shouli Yan,et al.  A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 µm CMOS , 2009, IEEE J. Solid State Circuits.

[7]  Ho-Jin Park,et al.  26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[8]  Nan Sun,et al.  A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOS , 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

[9]  Nan Sun,et al.  A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique , 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

[10]  R.W. Brodersen,et al.  A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS , 2006, IEEE Journal of Solid-State Circuits.

[11]  Robert W. Brodersen,et al.  A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS , 2006 .

[12]  Rui Paulo Martins,et al.  A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure , 2012, 2012 Symposium on VLSI Circuits (VLSIC).