A parallel simulator for performance modelling of broadband telecommunication networks

This paper describes the structure of a parallel simulator developed to investigate the performance of broadband telecommunication networks. The simulator hardware is based on a reconfigurable array of Inmos transputers. The software haa a layered architecture and issues of efficient communication, deadlock avoidance and message routeing have been addressed. The synchronization mechanism used is conservative, bssed on the Chandy-Misra model, and exploits lookahead. The speed-up results are almost linear when compared with the same parallel simulation run on a single transputer and are still impressive when compared wit h an optimized single processor version.

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