Delay test effectiveness evaluation of LSSD-Based VLSI logic circuits

Delay testing of VLSI logic chips has become critical to the quality of VLSI products. Data from failure analysis showed that small-size defects are more likely to occur than large size defects. These small-size defects are mainly responsible for delay defects that cause potentail system failure (1,2). At chip level, various delay test generation methods were developed (3,4) to consider delay faults either in the gate level or path level. Questions were raised (5,6) concerning the accuracy of the delay test effectiveness evaluation methods used in the conventional approach (7,8). It was shown that defect level, system sensitivity and tester accuracy are major factors in determining the quaIity of delay tests. In other words, a 100 percent delay test coverage obtained from conventional test generators and simulators does not guamntee a sufficient delay test quality.