Optimized Integration of Test Compression and Sharing for SOC Testing

The increasing test data volume needed to test core-based system-on-chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a constraint logic programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC '02 benchmark designs

[1]  Erik Jan Marinissen,et al.  Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[2]  Nur A. Touba,et al.  An efficient test vector compression scheme using selective Huffman coding , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Petru Eles,et al.  SOC Test Scheduling with Test Set Sharing and Broadcasting , 2005, 14th Asian Test Symposium (ATS'05).

[4]  Erik Jan Marinissen,et al.  A set of benchmarks for modular testing of SOCs , 2002, Proceedings. International Test Conference.

[5]  Erik Larsson,et al.  An Architecture for Combined Test Data Compression and Abort-on-Fail Test , 2007, 2007 Asia and South Pacific Design Automation Conference.

[6]  Yervant Zorian,et al.  Wrapper design for embedded core test , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[7]  Nicolas Beldiceanu,et al.  Constraint Logic Programming , 1997 .

[8]  Michael Gössel,et al.  On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture , 2006, Eleventh IEEE European Test Symposium (ETS'06).

[9]  Mark Mohammad Tehranipoor,et al.  Nine-coded compression technique for testing embedded cores in SoCs , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Steven S. Lumetta,et al.  X-tolerant test response compaction , 2005, IEEE Design & Test of Computers.

[11]  Erik Jan Marinissen,et al.  Test scheduling for modular SOCs in an abort-on-fail environment , 2005, European Test Symposium (ETS'05).

[12]  Kuen-Jong Lee,et al.  Broadcasting test patterns to multiple circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Krishnendu Chakrabarty,et al.  System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Hideo Ito,et al.  Concurrent Core Test for SOC Using Shared Test Set and Scan Chain Disable , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[15]  Krishnendu Chakrabarty,et al.  A unified approach to reduce SOC test data volume, scan power and testing time , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Kohei Miyase,et al.  On identifying don't care inputs of test patterns for combinational circuits , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).