Power Optimization in Domino Circuits using Stacked Transistors

In this work low leakage and high noise immunity do mino circuit is analysed. Usually power and noise immunity are optimized at the expense of reduced sp eed. The domino circuit described has negligible sp eed degradation. The circuit improves the noise immunit y by comparing the pull up network current with the worst case leakage current. The logic implementation network i s separated from the keeper transistor by current c omparison stage in which the current of the pull up network i s compared against the worst case leakage current. The contention between the keeper transistor and pull down network is greatly reduced by this method. The dynamic nod e is isolated from logic implementation network and hence the parasitic capacitance on the dynamic node is greatly reduced. Since capacitance is reduced the loss in s peed due to additional transistors is compensated. Because of reduced parasitic capacitance small keepers are eno ugh to design faster circuits. A footer transistor is employed in diode configuration which further reduces leakage c urrent.