High-efficiency multiple 4×4 and 8×8 inverse transform design with a cost-effective unified architecture for multistandard video decoders

This study developed multiple-inverse transform-based fast algorithms and a hardware-sharing design for 4×4 and 8×8 inverse transforms in H.264/AVC, VC-1, HEVC, and AVS standards for 8×8 inverse discrete cosine transforms in MPEG-1/2/4 schemes. The 4×4 VP8 inverse transform was developed using cost-effective hardware suitable for multistandard video decoding applications. Matrix factorizations were employed to realize the proposed ID hardware-sharing transform scheme by using only shifters and adders. Compared with the directly combined fast algorithms without hardware-sharing functionality, the proposed architecture reduces the number of shifters and adders by 50% and 75%, respectively. Compared with previous multistandard transform designs, the proposed architecture supports more transform modes. Furthermore, it exhibits fewer normalized gate counts and greater normalized hardware efficiency. Implementing VLSI enables the proposed hardware-sharing architecture for inverse transforms to achieve real-time video decoding at a resolution of 1920×1080p and a frame speed of 60 Hz.

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