High Correlative Low Power Test Pattern Generator Using a Transition Monitoring Window

This paper presents a new low power BIST TPG scheme to make high correlative test pattern. It uses a transition monitoring window (TMW) that is comprised of a combination circuit block and a MUX. When random test patterns are generated by an LFSR, transitions of those patterns satisfy pseudo-random gaussian distribution. The proposed technique represses transitions of patterns using a k-value which is a standard that is obtained from the distribution of TMW to observe over transitive patterns causing high power dissipation in a scan chain. Experimental results show about 60% transition reduction without performance loss in ISCAS’89 benchmark circuits that have large number scan inputs.

[1]  Malgorzata Marek-Sadowska,et al.  Star test: the theory and its applications , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Irith Pomeranz,et al.  A low power pseudo-random BIST technique , 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

[3]  Seongmoon Wang Generation of low power dissipation and high fault coverage patterns for scan-based BIST , 2002, Proceedings. International Test Conference.

[4]  Seongrnoon Wang,et al.  Low hardware overhead scan based 3-weight weighted random BIST , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[5]  Kaushik Roy,et al.  Peak power reduction in low power BIST , 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

[6]  Li Xiaowei,et al.  A low power BIST TPG design , 2003, ASICON 2003.

[7]  Sying-Jyan Wang,et al.  A reseeding technique for LFSR-based BIST applications , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[8]  Sandeep K. Gupta,et al.  DS-LFSR: a new BIST TPG for low heat dissipation , 1997, Proceedings International Test Conference 1997.

[9]  Kaushik Roy,et al.  POWERTEST: a tool for energy conscious weighted random pattern testing , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[10]  Sandeep K. Gupta,et al.  LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[11]  João Paulo Teixeira,et al.  Low Power BIST by Filtering Non-Detecting Vectors , 1999, European Test Workshop 1999 (Cat. No.PR00390).

[12]  Kaushik Roy,et al.  A technique to reduce power and test application time in BIST , 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

[13]  Atul K. Jain,et al.  Minimizing power consumption in scan testing: pattern generation and DFT techniques , 2004 .

[14]  Chulhee Lee,et al.  Perceptual Video Quality Analysis in the Modified Wavelet Domain , 2005 .

[15]  Cheol-Hong Moon,et al.  자동 윤곽 제어를 위한 FPGA 구현 , 2005 .

[16]  Mehrdad Nourani,et al.  Low power pattern generation for BIST architecture , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[17]  Yervant Zorian,et al.  A distributed BIST control scheme for complex VLSI devices , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.