A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications

A 10b two-stage pipeline ADC implemented in a 0.13mum CMOS operates at dual sampling clock rates of 25MS/s and 10MS/s based on a switched-bias power-reduction technique for low-power system applications. The prototype ADC shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling rates up to 25MS/s. The ADC occupies an active die area of 0.8mm2 and consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s, respectively, at a 1.2V supply

[1]  Robert G. Meyer,et al.  Analysis and Design of Analog Integrated Circuits , 1993 .

[2]  Phillip E Allen,et al.  CMOS Analog Circuit Design , 1987 .

[3]  Dong-Young Chang,et al.  A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique , 2003 .

[4]  Seung-Hoon Lee,et al.  Acquisition time minimisation techniques for high-speed analogue signal processing , 1999 .

[5]  Byung-Moo Min,et al.  A 69 mW 10 b 80 MS/s pipelined CMOS ADC , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[6]  Hae-Seung Lee,et al.  A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[7]  Dong-Young Chang,et al.  Design techniques for a low-power low-cost CMOS A/D converter , 1998 .