Research and analysis of routing algorithms for NoC

The Network-on-Chip has been recognized as a paradigm to solve System-on-Chip (SoC) design challenges. The routing algorithm is one of key researches of a NoC design. Its importance and effect on the performance of the network is accordingly cardinal. High-performance, load-blance, deadlock-free and livelock-free, fault-tolerant are the desirable properties of a routing algorithm for NoC. In this paper, we summarize routing algorithms used for NoC by simply comparison and analysis,and give the merits and demerits of some routing algorithms.

[1]  Maurizio Palesi,et al.  Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions , 2006, 9th EUROMICRO Conference on Digital System Design (DSD'06).

[2]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[3]  Vincenzo Catania,et al.  Application Specific Routing Algorithms for Networks on Chip , 2009, IEEE Transactions on Parallel and Distributed Systems.

[4]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[5]  Partha Pratim Pande,et al.  Performance evaluation and design trade-offs for network-on-chip interconnect architectures , 2005, IEEE Transactions on Computers.

[6]  Martin Radetzki,et al.  Fault-tolerant architecture and deflection routing for degradable NoC switches , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[7]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[8]  Wolfgang Trumler,et al.  Self-optimized Routing in a Network on-a-Chip , 2008, BICC.

[9]  David Blaauw,et al.  A highly resilient routing algorithm for fault-tolerant NoCs , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[10]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[11]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[12]  Ahmad Patooghy,et al.  Complement routing: A methodology to design reliable routing algorithm for Network on Chips , 2010, Microprocess. Microsystems.

[13]  Camel Tanougast,et al.  A new deadlock-free fault-tolerant routing algorithm for NoC interconnections , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[14]  Partha Pratim Pande,et al.  Design of a switch for network on chip applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[15]  Mahmut T. Kandemir,et al.  Fault tolerant algorithms for network-on-chip interconnect , 2004, IEEE Computer Society Annual Symposium on VLSI.

[16]  Wolfgang Rosenstiel,et al.  Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures , 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

[17]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[18]  Huaxi Gu,et al.  Quality of service routing algorithm in the torusbased network on chip , 2009, 2009 IEEE 8th International Conference on ASIC.

[19]  T. Dumitras,et al.  Towards on-chip fault-tolerant communication , 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

[20]  Mohsen Nickray,et al.  Adaptive routing using context-aware agents for networks on chips , 2009, 2009 4th International Design and Test Workshop (IDT).

[21]  Axel Jantsch,et al.  FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip , 2010, 23rd IEEE International SOC Conference.

[22]  Lionel M. Ni,et al.  The turn model for adaptive routing , 1998, ISCA '98.

[23]  Lionel M. Ni,et al.  A survey of wormhole routing techniques in direct networks , 1993, Computer.

[24]  Alain Greiner,et al.  A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[25]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[26]  Axel Jantsch,et al.  A framework for designing congestion-aware deterministic routing , 2010, NoCArc '10.

[27]  José Duato,et al.  A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks , 1993, IEEE Trans. Parallel Distributed Syst..

[28]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[29]  Lionel M. Ni,et al.  The Turn Model for Adaptive Routing , 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.