ASIM-An Asynchronous Architectural Level Simulator
暂无分享,去创建一个
[1] Erik Brunvand,et al. Fred: an architecture for a self-timed decoupled computer , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[2] Peter H. Welch,et al. CSP Networking for Java (JCSP.net) , 2002, International Conference on Computational Science.
[3] Jeremy M. R. Martin,et al. Formal Analysis of Concurrent Java Systems , 2000 .
[4] Erik Brunvand,et al. An Integrated Environment for the Design and Simulation of Self-Timed Systems , 1991, VLSI.
[5] W. F. Richardson,et al. Architectural considerations for a self-timed decoupled processor , 1996 .
[6] Alain J. Martin. Compiling communicating processes into delay-insensitive VLSI circuits , 2005, Distributed Computing.
[7] C. A. R. Hoare,et al. Communicating sequential processes , 1978, CACM.
[8] Marly Roncken,et al. The VLSI-programming language Tangram and its translation into handshake circuits , 1991, Proceedings of the European Conference on Design Automation..
[9] Erik Brunvand,et al. Translating concurrent programs into delay-insensitive circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[10] Andrew Bardsley,et al. Compiling the language Balsa to delay insensitive hardware , 1997 .
[11] Todd M. Austin,et al. The SimpleScalar tool set, version 2.0 , 1997, CARN.
[12] Mark Horowitz,et al. IRSIM: An Incremental MOS Switch-Level Simulator , 1989, 26th ACM/IEEE Design Automation Conference.
[13] Erik Brunvand,et al. A comparison of self-timed design using FPGA, CMOS, and GaAs technologies , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.