Balancing clock skew for near-threshold multi-voltage multi-power-mode designs using a multi-stage PMAB approach

In near-threshold multi-voltage designs, large clock skew occurs between different voltage domains. Several works of power-mode-aware buffer (PMAB) were dedicated to diminish this clock skew. However, they were commonly based on circumstances that each power domain had at most two supply voltages. In this brief, we propose a multi-stage PMAB approach to diminish clock skew for multi-voltage multi-power-mode designs. We implement this approach in a design that has a micro-processor operating under a voltage varying from 0.6V to 0.99V. The result shows our approach limited clock skew within 0.21ns for all power modes, and consumed 11% less resource for hold fixing, compared to the latest proposal.