Design of low-power low-area asynchronous iterative multiplier

[1]  Hanho Lee A power-aware scalable pipelined Booth multiplier , 2004, IEEE International SOC Conference, 2004. Proceedings..

[2]  Peter A. Beerel,et al.  Low Power and Energy Efficient Asynchronous Design , 2007, J. Low Power Electron..

[3]  Jan M. Rabaey,et al.  A 0.25 V 460 nW Asynchronous Neural Signal Processor With Inherent Leakage Suppression , 2013, IEEE Journal of Solid-State Circuits.

[4]  Laxmi Kumre,et al.  Low-power less-area bypassing-based multiplier design , 2017, 2017 International Conference on Inventive Computing and Informatics (ICICI).

[5]  Chen-Yi Lee,et al.  A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems , 2008, IEEE Journal of Solid-State Circuits.

[6]  Shiann-Rong Kuang,et al.  Design of Power-Efficient Configurable Booth Multiplier , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Yang Guo,et al.  An efficient floating-point multiplier for digital signal processors , 2014, IEICE Electron. Express.

[8]  Anselmo Lastra,et al.  A scalable counterflow-pipelined asynchronous radix-4 Booth multiplier , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[9]  Yijun Liu,et al.  The design of a low power asynchronous multiplier , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[10]  Chen-Yi Lee,et al.  A dynamic scaling FFT processor for DVB-T applications , 2004 .

[11]  Ran Ginosar,et al.  Minimal Energy Asynchronous Dynamic Adders , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Luca Benini,et al.  An Event-Driven Ultra-Low-Power Smart Visual Sensor , 2016, IEEE Sensors Journal.

[13]  Meng-Chou Chang,et al.  Low-Power Asynchronous NCL Pipelines With Fine-Grain Power Gating and Early Sleep , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[14]  Milos D. Ercegovac,et al.  High-performance low-power left-to-right array multiplier design , 2005, IEEE Transactions on Computers.

[15]  Atul,et al.  Design of low power fixed-width multiplier with row bypassing , 2012, IEICE Electron. Express.

[16]  Peter A. Beerel,et al.  An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Hossein Pedram,et al.  Design of dual threshold voltages asynchronous circuits , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

[18]  Amine Bermak,et al.  32 Bit $\times\,$32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Yuan-Sun Chu,et al.  A Low-Power Multiplier With the Spurious Power Suppression Technique , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Bah-Hwee Gwee,et al.  Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Kyoung-Rok Cho,et al.  A Low-Power Implementation of Asynchronous 8051 Employing Adaptive Pipeline Structure , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[22]  Frank Lane,et al.  Low Power QDI Asynchronous FFT , 2016, 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).

[23]  Bernard Brezzo,et al.  TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  K. Bala Sindhuri,et al.  Design of delay efficient modified 16 bit Wallace multiplier , 2016, 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT).