Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem
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[1] Hiroto Yasuura,et al. Redundant Coding for Local Computability , 1987 .
[2] Ernest A. Brickell. A survey of hardware implementations of RSA (abstract) , 1989, CRYPTO 1989.
[3] Ernest F. Brickell,et al. A Survey of Hardware Implementation of RSA (Abstract) , 1989, CRYPTO.
[4] Algirdas Avizienis,et al. Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..
[5] Hiroto Yasuura,et al. High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree , 1985, IEEE Transactions on Computers.
[6] Adi Shamir,et al. A method for obtaining digital signatures and public-key cryptosystems , 1978, CACM.
[7] Ernest F. Brickell,et al. A Fast Modular Multiplication Algorithm With Application To Two Key Cryptography , 1982, CRYPTO.
[8] Naofumi Takagi. Studies on Hardware Algorithms for Arithmetic Operations with a Redundant Binary Representation , 1988 .
[9] Hikaru Morita,et al. A Fast Modular-multiplication Algorithm based on a Higher Radix , 1989, CRYPTO.