A transformational approach to formal digital system design
暂无分享,去创建一个
[1] Alonzo Church,et al. A formulation of the simple theory of types , 1940, Journal of Symbolic Logic.
[2] I. G. BONNER CLAPPISON. Editor , 1960, The Electric Power Engineering Handbook - Five Volume Set.
[3] Michael J. C. Gordon,et al. Edinburgh LCF: A mechanised logic of computation , 1979 .
[4] Alice C. Parker,et al. An Abstract Model of Behavior for Hardware Descriptions , 1983, IEEE Transactions on Computers.
[5] Mary Sheeran. UpsilonFP : An algebraic VLSI design language , 1983 .
[6] Harry G. Barrow. Proving the Correctness of Digital Hardware Designs , 1983, AAAI.
[7] Ben C. Moszkowski,et al. Executing temporal logic programs , 1986, Seminar on Concurrency.
[8] Michael J. C. Gordon,et al. Why higher-order logic is a good formalism for specifying and verifying hardware , 1985 .
[9] Ben C. Moszkowski,et al. A Temporal Logic for Multilevel Reasoning about Hardware , 1985, Computer.
[10] George J. Milne,et al. CIRCAL and the representation of communication, concurrency, and time , 1985, TOPL.
[11] Edmund M. Clarke,et al. Automatic Verification of Sequential Circuits Using Temporal Logic , 1986, IEEE Transactions on Computers.
[12] Editors , 1986, Brain Research Bulletin.
[13] David A. Schmidt,et al. Denotationaisemantics: a methodology for language development , 1986 .
[14] Lawrence C. Paulson,et al. Logic and computation - interactive proof with Cambridge LCF , 1987, Cambridge tracts in theoretical computer science.
[15] Zebo Peng. A formal methodology for automated synthesis of VLSI systems , 1987 .
[16] Peter Bishop,et al. Designing Asics , 1988 .
[17] Stephen J. Garland,et al. Verification of VLSI Circuits Using LP , 1988 .
[18] Tom Melham,et al. Abstraction Mechanisms for Hardware Verification , 1988 .
[19] Roger William Stephen Hale. Programming in temporal logic , 1988 .
[20] Paliath Narendran,et al. Formal verification of the Sobel image processing chip , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[21] Raymond T. Boute,et al. Systems semantics: principles, applications, and implementation , 1988, TOPL.
[22] Avra Cohn,et al. A Proof of Correctness of the Viper Microprocessor: The First Level , 1988 .
[23] Shiu-Kai Chin. Combining Engineering Vigor with Mathematical Rigor , 1989, Hardware Specification, Verification and Synthesis.
[24] Roger Lipsett,et al. VHDL: hardware description and design , 1989 .
[25] Jonathan S. Ostroff,et al. Real-time temporal logic decision procedures , 1989, [1989] Proceedings. Real-Time Systems Symposium.
[26] N. Daeche,et al. Formal Synthesis of Digital Systems , 1989 .
[27] Michael P. Fourman. Formal system design , 1989 .
[28] Avra Cohn. Correctness properties of the Viper block model: the second level , 1989 .
[29] Tom Melham,et al. Formalizing abstraction mechanisms for hardware verification in higher order logic , 1990 .
[30] Bishop C. Brock,et al. A Formal Introduction to a Simple HDL , 1990 .
[31] J. Staunstrup. Formal Methods for VLSI Design: IFIP Wg10.5 Lecture Notes , 1990 .
[32] Alice C. Parker,et al. The high-level synthesis of digital systems , 1990, Proc. IEEE.
[33] Donald E. Thomas,et al. The Verilog® Hardware Description Language , 1990 .
[34] H. Eveking. Experience in Designing Formally Verifiable HDL's , 1991 .
[35] Alain J. Martin. Synthesis of Asynchronous VLSI Circuits , 1991 .
[36] Rachel Cardell-Oliver. On The Use Of The HOL System For Protocol Verification , 1991, 1991., International Workshop on the HOL Theorem Proving System and Its Applications.
[37] Holger Busch. Proof-based transformation of formal hardware models , 1991 .
[38] X. Wang,et al. Formalization Of VHDL Synthesis Procedure In Higher-order Logic , 1991, 1991., International Workshop on the HOL Theorem Proving System and Its Applications.
[39] John Herbert,et al. Dealing With Temporal Complexity in hardware verification , 1991, 1991., International Workshop on the HOL Theorem Proving System and Its Applications.
[40] David Kinniment,et al. Correct interactive transformational synthesis of DSP hardware , 1991, Proceedings of the European Conference on Design Automation..
[41] J. D. Morison,et al. A Formal Definition of the Static Semantics of Ella's Core , 1991 .
[42] D. Suk. Hardware synthesis in constructive type theory , 1991 .
[43] Michael P. Fourman,et al. Integration of Formal Methods with System Design , 1991, VLSI.
[44] M. Gordon,et al. The Hol Veriication of Ella Designs 1 , 1991 .
[45] Laurence Pierre,et al. From a HDL Description to Formal Proof Systems: Principles and Mechanization , 1991 .
[46] Jim Grundy,et al. Window Inference In The HOL System , 1991, 1991., International Workshop on the HOL Theorem Proving System and Its Applications.
[47] Holger Busch,et al. Proof-aided design of verified hardware , 1991, 28th ACM/IEEE Design Automation Conference.
[48] Edmund M. Clarke,et al. A language for compositional specification and verification of finite state hardware controllers , 1991 .
[49] Roger Hale. Reasoning About Software , 1991, 1991., International Workshop on the HOL Theorem Proving System and Its Applications.
[50] Daniel D. Gajski,et al. High ― Level Synthesis: Introduction to Chip and System Design , 1992 .
[51] W. Hunt,et al. A formal HDL and its use in the FM9001 verification , 1992, Philosophical Transactions of the Royal Society of London. Series A: Physical and Engineering Sciences.
[52] Gabriele Umbreit. Providing a VHDL-interface for proof systems , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.
[53] Ulrich Lauther. Introduction to Synthesis , 1992 .
[54] John Van Tassel. A Formalisation of the VHDL Simulation Cycle , 1992, TPHOLs.
[55] Richard J. Boulton,et al. Experience with Embedding Hardware Description Languages in HOL , 1992, TPCD.
[56] F. Hanna,et al. Dependent types and formal synthesis , 1992, Philosophical Transactions of the Royal Society of London. Series A: Physical and Engineering Sciences.
[57] Guy Durrieu,et al. Transe: An Experimental Transformation Assistant for Digital Circuit Design , 1992, Designing Correct Circuits.
[58] Petru Eles,et al. Compiling VHDL into a high-level synthesis design representation , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.
[59] Jim Grundy,et al. A Window Inference Tool for Refinement , 1992, Refine.
[60] John Staples,et al. Formalizing a Hierarchical Structure of Practical Mathematical Reasoning , 1993, J. Log. Comput..
[61] Graham Hutton,et al. The Ruby Interpreter , 1993 .