SEU tolerant SRAM cell

Modern integrated circuits require careful attention to the soft errors resulting into bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred to as single-event upsets (SEUs), will become more severe for future technologies. In this paper we propose a novel 10T SEU tolerant SRAM cell design. Our SRAM cell is area efficient in comparison with the earlier proposals. Simulation results show that the proposed cell is robust as it does not flip even for a transient pulse with four times the Qcrit of a standard 6T SRAM cell.

[1]  Yong-Bin Kim,et al.  A novel design technique for soft error hardening of Nanoscale CMOS memory , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

[2]  Hideo Ito,et al.  Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[3]  John P. Hayes,et al.  An Analysis Framework for Transient-Error Tolerance , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[4]  Rong Luo,et al.  A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Naresh R. Shanbhag,et al.  Sequential Element Design With Built-In Soft Error Resilience , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  André DeHon,et al.  Fault Secure Encoder and Decoder for NanoMemory Applications , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Mehdi Baradaran Tahoori,et al.  An accurate SER estimation method based on propagation probability [soft error rate] , 2005, Design, Automation and Test in Europe.

[8]  Kewal K. Saluja,et al.  On techniques for handling soft errors in digital circuits , 2010, 2010 IEEE International Test Conference.

[9]  Feng Shi,et al.  Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Dan Alexandrescu,et al.  Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[11]  G. C. Messenger,et al.  Collection of Charge on Junction Nodes from Ion Tracks , 1982, IEEE Transactions on Nuclear Science.