An On-Line Square Root Algorithm

In this correspondence a systematic derivation of an on-line square root algorithm is presented. The algorithm operates on variables represented in the normalized radix r floating-point system in a digit-by-digit fashion with an on-line delay of 1. The approach used in deriving the square root algorithm is described in detail. The basic characteristics of hardware-level implementation are also discussed.

[1]  A. J. Atrubin A One-Dimensional Real-Time Iterative Multiplier , 1965, IEEE Trans. Electron. Comput..

[2]  D.E. Atkins Design of the Arithmetic Units of ILLIAC III: Use of Redundancy and Higher Radix Methods , 1970, IEEE Transactions on Computers.

[3]  Daniel E. Atkins,et al.  Introduction to the Role of Redundancy in Computer Arithmetic , 1975, Computer.

[4]  Mary Jane Irwin An arithmetic unit for on-line computation. , 1977 .

[5]  Gernot Metze,et al.  Minimal Square Rooting , 1965, IEEE Trans. Electron. Comput..

[6]  Abdolali Gorji-Sinaki Error-coded algorithms for on-line arithmetic , 1981 .

[7]  Algirdas Avizienis,et al.  Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design , 1971, IEEE Transactions on Computers.

[8]  Algirdas Avizienis,et al.  On a Flexible Implementation of Digital Computer Arithmetic , 1962, IFIP Congress.

[9]  James E. Robertson,et al.  A New Class of Digital Division Methods , 1958, IRE Trans. Electron. Comput..

[10]  Kishor S. Trivedi,et al.  On-line algorithms for division and multiplication , 1975, 1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH).

[11]  Milos D. Ercegovac,et al.  An on-line square rooting algorithm , 1978, 1978 IEEE 4th Symposium onomputer Arithmetic (ARITH).

[12]  Milos D. Ercegovac A general method for evaluation of functions and computations in a digital computing , 1975, 1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH).

[13]  A. Avizeinis,et al.  Signed Digit Number Representations for Fast Parallel Arithmetic , 1961 .

[14]  T. C. Chen,et al.  Multiple Addition by Residue Threshold Functions and Their Representation by Array Logic , 1973, IEEE Transactions on Computers.

[15]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[16]  Milos D. Ercegovac A General Hardware-Oriented Method for Evaluation of Functions and Computations in a Digital Computer , 1977, IEEE Transactions on Computers.