论文信息 - Influence of gate length on ESD-performance for deep sub micron CMOS technology

Influence of gate length on ESD-performance for deep sub micron CMOS technology

The ESD performance of grounded-gate nMOS protection structures has been observed for a standard 0.25 /spl mu/m CMOS epitaxial layer based technology. The shortest gate lengths show unexpectedly lower ESD thresholds, leading to an optimum performance for longer gate length devices attributed to the trade-off between power dissipation and melt volume of the parasitic bipolar device.

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