SET Susceptibility Analysis of Clock Tree and Clock Mesh Topologies

Clock distribution networks represent one of the most important signals in a synchronous integrated circuit, this signal may be altered by radiation effects and generate an abnormal behavior in the system. In this work we analyzed two types of clock distribution network using the same circuit to know which of one is more sensitive to radiation threats. Using a case study we compare clock tree with clock mesh. Finally we found that clock mesh topology is more sensitive to radiation effects in comparison with traditional tree distribution. This may occur because clock mesh has a uniform distribution of capacitance and this allows a good distribution of the signal even to transient pulse.

[1]  K.A. Jenkins,et al.  A clock distribution network for microprocessors , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[2]  Ming Zhang,et al.  A CMOS design style for logic circuit hardening , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[3]  Ricardo Reis,et al.  SET susceptibility estimation of clock tree networks from layout extraction , 2012, 2012 13th Latin American Test Workshop (LATW).

[4]  Eby G. Friedman,et al.  Clock distribution networks in synchronous digital integrated circuits , 2001, Proc. IEEE.

[5]  Srivatsan Chellappa,et al.  A 90-nm Radiation Hardened Clock Spine , 2011, IEEE Transactions on Nuclear Science.

[6]  R. Lacoe.  Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology , 2008, IEEE Transactions on Nuclear Science.

[7]  L. Dominik,et al.  System mitigation techniques for single event effects , 2008, 2008 IEEE/AIAA 27th Digital Avionics Systems Conference.

[8]  Gwan S. Choi,et al.  SEU hardened clock regeneration circuits , 2009, 2009 10th International Symposium on Quality Electronic Design.

[9]  D. Munteanu,et al.  Modeling and Simulation of Single-Event Effects in Digital Devices and ICs , 2008, IEEE Transactions on Nuclear Science.

[10]  Fernanda Gusmão de Lima Kastensmidt,et al.  Accurate and computer efficient modelling of single event transients in CMOS circuits , 2007, IET Circuits Devices Syst..

[11]  L. Wissel,et al.  Flip-Flop Upsets From Single-Event-Transients in 65 nm Clock Circuits , 2009, IEEE Transactions on Nuclear Science.

[12]  Eduardo Chielle,et al.  Soft-Error Probability Due to SET in Clock Tree Networks , 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

[13]  Niccolò Battezzati,et al.  Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs , 2009, 2009 15th IEEE International On-Line Testing Symposium.

[14]  A. Mallajosyula,et al.  A Robust Single Event Upset Hardened Clock Distribution Network , 2008, 2008 IEEE International Integrated Reliability Workshop Final Report.