CChemical-mechanical polishing (CMP) is a technique used in very deep-submicron VLSI manufacturing to achieve uniformity in long range oxide planarization. Post-CNIP topography is highly related to local spatial pattern density in layout. To change local pattern density, and thus ensure post-CMP planarization, dummy features are placed in layout. The only known previously published algorithm for dummy feature placement is based oil a very simple and inadequate model. This paper is based on a closed-form analytical model for inter-level dielectric thickness in CMP process by B. Stine et al. and a model for effective local layout pattern density by D. Ouma et al. Those two models accurately describe the relation between local pattern density and post-CMP planarization. This paper uses those two models to solve the dummy feature placement problem of a single layer in the fixed-dissection regime. An experiment, conducted with real industry design data, gives excellent results by reducing post-CMP topography variation from 753A to 169A.
[1]
C. Burrus,et al.
DFT/FFT and Convolution Algorithms: Theory and Implementation
,
1991
.
[2]
I. Ali,et al.
Chemical-mechanical polishing of interlayer dielectric: a review
,
1994
.
[3]
D. Boning,et al.
An integrated characterization and modeling methodology for CMP dielectric planarization
,
1998,
Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).
[4]
A. Dengi,et al.
A two-dimensional low pass filter model for die-level topography variation resulting from chemical mechanical polishing of ILD films
,
1999,
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).