Computational properties of LDI/LDD lattice filters

In this paper, a new modified LDI/LDD allpass filler is presented, which is well suited for high throughput applications. It has one multiplier and three adders in the critical loop, and can be implemented in hardware with fewer adders than, for example, wave digital allpass filters. We also propose a maximally fast scheduling of the second-order LDI/LDD allpass filter, where cyclic scheduling is used. Some results regarding implementation of the LDI/LDD lattice filter in an FPGA are presented. Bit-serial arithmetics are considered.

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