For the first time, thermal atomic layer etching (ALE) on InGaAs-based III-V heterostructures is demonstrated. Also, we report the first transistors fabricated by the thermal ALE technique in any semiconductor system. We further highlight one unique advantage of thermal ALE: its integration with atomic layer deposition (ALD) in a single vacuum chamber. Using in situ ALE-ALD, we have fabricated the most aggressively scaled self-aligned In<inf>0.53</inf>Ga<inf>0.47</inf>As n-channel FinFETs to date, featuring sub-5 nm fin widths. The narrowest FinFET with <tex>$\mathrm{W_{f}}=2.5$</tex> nm and <tex>$\mathrm{L_{g}} =60$</tex> nm shows <tex>$\mathrm{g}_{\mathrm{m}}=0.85\ \text{mS}/\mu \mathrm{m}$</tex> at <tex>$\mathrm{V}_{\text{ds}}=0.5$</tex> V. Devices with <tex>$\mathrm{W_{f}}=18$</tex> nm and <tex>$\mathrm{L_{g}}=60$</tex> nm demonstrate <tex>$\mathrm{g_{m}}=1.9\ \ \text{mS}/\mu \mathrm{m}$</tex> at <tex>$\mathrm{V}_{\text{ds}}=0.5$</tex> V. Subthreshold swings averaging <tex>$\mathrm{S}_{\text{lin}}=70$</tex> mV/dec and <tex>$\mathrm{S}_{\text{sat}}=74$</tex> mV/dec across the entire range of W<inf>f</inf>, at minimum <tex>$\mathrm{L_{g}}=60$</tex> nm have been obtained. These are all record results. The transistors demonstrated here show an average 60% gm improvement over devices fabricated through conventional techniques. These results suggest a very high-quality MOS interface obtained by the in situ ALE-ALD process.