A 13-bit band-pass double-sampling delta-sigma A/D converter for 5 MHz signals

This work introduces a fully differential double-sampled fourth-order switched-capacitor band-pass sigma-delta modulator for analog-to-digital conversion of 5-MHz intermediate frequency (IF). The used architecture is based on a double-sampled switched-capacitor delay circuit. We attempt to describe the design procedure and system level simulations in detail. The single-loop one-bit modulator operates at a clock frequency of 10 MHz creating an effective sampling rate of 20 MHz. The modulator implements its constituent resonators by chopping the signal at the IF (fs/4). The modulator has been simulated in a 0.35-/spl mu/m CMOS process. Using a 3.3-V power supply it achieves a dynamic range of 75-dB over a 100 KHz signal bandwidth.