Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design

Several regular circuit structures are proposed. They provide alternatives to the widely used standard-cell structure and have better predictability and a simpler design methodology. A regular global routing scheme is developed. A design flow for use with of all these regular fabrics is discussed.

[1]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[2]  Alberto L. Sangiovanni-Vincentelli,et al.  Multiple-Valued Minimization for PLA Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Robert K. Brayton,et al.  River PLAs: a regular circuit structure , 2002, DAC '02.

[4]  Y. B. Dhong,et al.  High speed CMOS POS PLA using predischarged OR array and charge sharing AND array , 1992 .

[5]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[6]  Robert K. Brayton,et al.  A force-directed macro-cell placer , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[7]  Jan M. Rabaey,et al.  Limitations and challenges of computer-aided design technology for CMOS VLSI , 2001, Proc. IEEE.

[8]  Robert K. Brayton,et al.  Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[9]  Jason Cong,et al.  Buffer block planning for interconnect planning and prediction , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Robert K. Brayton,et al.  Multilevel logic synthesis , 1990, Proc. IEEE.

[11]  Christos A. Papachristou,et al.  A design scheme for PLA-based control tables with reduced area and time-delay cost , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..