Fabrication of interface-modified ramp-edge junction on YBCO ground plane with multilayer structure

Abstract We examined the fabrication conditions to obtain high-quality ramp-edge Josephson junctions on a liquid-phase-epitaxy YBa2Cu3Oy (LPE-YBCO) ground plane, in particular, focusing on the fabrication of a suitable insulating layer on the ground plane and the post-annealing conditions to load oxygen to the ground plane. A (LaAlO3)0.3–(SrAl0.5Ta0.5O3)0.7 (LSAT) insulating film on the ground planes exhibited a conductance ranging from 10−4 to 10−8 S after deposition of an upper superconducting film, suggesting existence of some leak paths through the LSAT insulating layer. By introducing approximately 30 nm thick SrTiO3 (STO) buffer layers on both side of the LSAT insulating layer. We reproducibly obtained a conductance lower than 10−8 S. The dielectric constant of the STO/LSAT/STO layer was 32, which was slightly larger than that of the single LSAT layer. It was found that a very slow cooling rate of 1.0 °C/h in oxygen was needed to fully oxidize the ground plane through the STO/LSAT/STO insulating layers, while the oxidation time could be effectively reduced by introducing via holes in the insulating layer at an interval of 200 μm. Ramp-edge junctions on LPE-YBCO ground planes with STO/LSAT/STO insulating layers exhibited a 1σ-spread in Ic of 8% for 100-junction series-arrays and a sheet inductance of 0.7 pH/□ at 4.2 K.