Approximate Logic Synthesis of Very Large Boolean Networks

For very large Boolean circuits most approximate logic synthesis techniques successively apply local approximation transformations affecting only a portion of the whole design. Hence, allowing such transformations to be implemented in polynomial time and to gain better control of the introduced error. A key issue here is to derive efficient techniques for selecting from all the possible portions of the design those more likely to yield better trade-offs between hardware resources and quality. Due to the likelihood of error masking growing with increasing circuit complexity, we expect the likelihood of a local transformation reaching-or being observable at-the primary outputs to decrease at a similar rate. Comparatively, the closer a portion undergoing a local transformation is to the primary outputs, the more likely the error introduced can be observed at the primary outputs. Based on this observation, this paper proposes a novel methodology for the selection of portions-or sub-functions-of Boolean circuits-represented by Boolean networks-for approximation according to their degree of connectivity with other portions of the design. Our selection criterion is based on that a Boolean sub-function shall be a better candidate for approximation when it drives many other sub-functions, especially those being driven by many other sub-functions. We introduce, integrate, and compare our connectivity-based selection methodology with a state-of-the-art approximate logic synthesis framework. Experimental results show that our selection technique yields better trade-offs between hardware resources and accuracy of the resulting approximated circuits. Moreover, our technique is efficient and can speed up the design space exploration of the aforementioned framework.