A fourth order continuous-time complex sigma-delta ADC for low-IF GSM and EDGE receivers

A low-power fourth order continuous-time complex /spl Sigma//spl Delta/ ADC has been designed and fabricated for low-IF (LIF) GSM and EDGE receivers in a 0.25 /spl mu/m CMOS technology. This ADC has a bandwidth of 270 kHz centered around-100 kHz. The dynamic range (DNR) is 82 dB at a sampling rate of 13 MHz even though the digital decimation filter and other blocks are active on the chip. The power consumption is 4.6 mW at 2 V supply. To our knowledge this ADC has the best performance, which has been reported so far with a complex /spl Sigma//spl Delta/ ADC for LIF mode GSM and EDGE receivers.

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