Scalable Verification of a Generic End-Around-Carry Adder for Floating-Point Units by Coq

Theorem proving has been demonstrated as a powerful technique for datapath verification. This paper considers a generic logic-level architecture of end-around-carry adder, which is extensively used in floating-point arithmetic. The architecture is component-based and parameterized for easy customization. The design architecture is formalized and verified in the mechanical theorem prover Coq. The scalable proof provides necessary underpinnings for verifying customized and new implementations.

[1]  Feng Liu,et al.  Formal Analysis of End-Around-Carry Adder in Floating-Point Unit , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  John J. Shedletsky Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder , 1977, IEEE Trans. Computers.

[3]  Xiao Yan Yu,et al.  A 5GHz+ 128-bit Binary Floating-Point Adder for the POWER6 Processor , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[4]  Thomas F. Melham Higher Order Logic and Hardware Verification , 1993, Cambridge Tracts in Theoretical Computer Science.

[5]  Hugo Herbelin,et al.  The Coq proof assistant : reference manual, version 6.1 , 1997 .

[6]  Adam Chlipala,et al.  Formal Verification of Hardware Synthesis , 2013, CAV.

[7]  Christine Paulin-Mohring,et al.  The coq proof assistant reference manual , 2000 .

[8]  Akhilesh Tyagi,et al.  A Reduced-Area Scheme for Carry-Select Adders , 1993, IEEE Trans. Computers.

[9]  Jean-Pierre Jouannaud,et al.  CoQMTU: A Higher-Order Type Theory with a Predicative Hierarchy of Universes Parametrized by a Decidable First-Order Theory , 2011, 2011 IEEE 26th Annual Symposium on Logic in Computer Science.

[10]  Feng Liu,et al.  Proofs of Correctness and Properties of Integer Adder Circuits , 2010, IEEE Transactions on Computers.

[11]  Michael J. C. Gordon,et al.  Why higher-order logic is a good formalism for specifying and verifying hardware , 1985 .

[12]  Eric M. Schwarz,et al.  Binary Floating-Point Unit Design , 2006 .

[13]  Qian Wang,et al.  Functional Verification of High Performance Adders in COQ , 2014, J. Appl. Math..

[14]  Jason Baumgartner,et al.  Automatic formal verification of fused-multiply-add FPUs , 2005, Design, Automation and Test in Europe.

[15]  Line Jakubiec,et al.  Certifying circuits in Type Theory , 2004, Formal Aspects of Computing.

[16]  D. Kroening,et al.  Formal Verification of a Basic Circuits Library , 2001 .

[17]  Xiao Yan Zhang,et al.  A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit , 2010, J. Signal Process. Syst..

[18]  Cheng-Chew Lim,et al.  Parallel prefix adder design , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[19]  Martin Kuefer High Performance Energy Efficient Microprocessor Design , 2016 .

[20]  Qian Wang,et al.  Semantics of Intensional Type Theory extended with Decidable Equational Theories , 2013, CSL.

[21]  G. Chen Formalization of a Parameterized Parallel Adder Within the Coq Theorem Prover , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.