Dynamic hardware multiplexing for coarse grain reconfigurable architectures

When designing a SoC, matching the required performances both in terms of processing power and power consumption tends to become more and more challenging. Moreover, since the range of targeted applications for every single product is widening rapidly, employing reconfigurable accelerators makes more and more sense to this purpose. Coarse grain reconfigurable architectures bring an alternative providing interesting performances / flexibility trade-offs over traditional approaches. This work presents an original method allowing to efficiently exploiting dynamically parallelism at both loop-level and task-level, which remains rarely used. This method called DHM (Dynamic Hardware Multiplexing) is based upon the use of a hardwired controller dedicated to the dynamical unroll of loops or scheduling of tasks. This work shows that significant performance improvements can be achieved through combining both intra and inter-task parallelism. Principles and validations are exposed through a case study on a coarse grain reconfigurable architecture, called Systolic Ring. The exposed method could be applied to any coarse and fine grain architectures.