Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies

Variation in transistor characteristics is increasing as CMOS transistors are scaled to nanometer feature sizes. This increase in transistor variability poses a serious challenge to the cost-effective utilization of scaled technologies. Meeting this challenge requires comprehensive and efficient approaches for variability characterization, minimization, and mitigation. This paper describes an efficient infrastructure for characterizing the various types of variation in transistor characteristics. A sample of results obtained from applying this infrastructure to a number of technologies at the 90-, 65-, and 45-nm nodes is presented. This paper then illustrates the impact of the observed variability on SRAM, analog and digital circuit blocks used in system-on-chip designs. Different approaches for minimizing transistor variation and mitigating its impact on product performance and yield are also described.

[1]  A. De Keersgieter,et al.  Layout impact on the performance of a locally strained PMOSFET , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[2]  J. Conner,et al.  Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors , 2006, 2006 International Electron Devices Meeting.

[3]  K. Bowman,et al.  Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance , 2000, IEEE Journal of Solid-State Circuits.

[4]  Dennis L. Young,et al.  Application of statistical design and response surface methods to computer-aided VLSI device design , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  P.R. Kinget.  Device mismatch and tradeoffs in the design of analog circuits , 2005, IEEE Journal of Solid-State Circuits.

[6]  G. Eneman,et al.  Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study , 2007, IEEE Transactions on Electron Devices.

[7]  Amitava Chatterjee,et al.  Correction to "Trench Isolation Step-Induced (TRISI) Narrow Width Effect on MOSFET" , 2002 .

[8]  Andrzej J. Strojwas,et al.  Exploring regular fabrics to optimize the performance-cost trade-off , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[9]  K. Ohuchi,et al.  Issues and optimization of millisecond anneal process for 45 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[10]  Chenming Hu,et al.  Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction , 2004, IEEE Transactions on Semiconductor Manufacturing.

[11]  A. Toriumi,et al.  Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's , 1994 .

[12]  S. Saini,et al.  Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0 . 1m MOSFET ’ s with Epitaxial and-Doped Channels , 1999 .

[13]  S. Saini,et al.  Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-/spl mu/m MOSFET's with epitaxial and /spl delta/-doped channels , 1999 .

[14]  N. Takahashi,et al.  Design for manufacturability characterization and optimization of mixed-signal IP , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[15]  T. Mizuno.  New channel engineering for sub-100 nm MOS devices considering both carrier velocity overshoot and statistical performance fluctuations , 2000 .

[16]  A.J. Strojwas.  Conquering Process Variability: A Key Enabler for Profitable Manufacturing in Advanced Technology Nodes , 2006, 2006 IEEE International Symposium on Semiconductor Manufacturing.

[17]  James D. Meindl,et al.  Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.

[18]  S. Minehane,et al.  Characterization and modeling of MOSFET mismatch of a deep submicron technology , 2003, International Conference on Microelectronic Test Structures, 2003..

[19]  H. Kimura,et al.  RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

[20]  Xiaojing Yang,et al.  Method for Fast and Accurate Calibration of Litho Simulator for Hot Spot Analysis , 2006, 2006 IEEE International Symposium on Semiconductor Manufacturing.

[21]  Michael R. Chernick,et al.  Variance Components Estimation: Mixed Models, Methodologies and Applications , 2002, Technometrics.

[22]  K. Ravindran,et al.  First-Order Incremental Block-Based Statistical Timing Analysis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  H. Pilo,et al.  An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage , 2007, IEEE Journal of Solid-State Circuits.

[24]  M. Tiebout,et al.  A 4GS/s 6b flash ADC in 0.13 /spl mu/m CMOS , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[25]  S.R. Nassif.  Within-chip variability analysis , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[26]  E. Ziegel.  Modern Mathematical Statistics , 1989 .

[27]  Costas J. Spanos,et al.  Fundamentals of Semiconductor Manufacturing and Process Control , 2006 .

[28]  S. Saxena,et al.  Test structures and analysis techniques for estimation of the impact of layout on MOSFET performance and variability , 2004, Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).

[29]  C. Hess,et al.  Device Array Scribe Characterization Vehicle Test Chip for Ultra Fast Product Wafer Variability Monitoring , 2007, 2007 IEEE International Conference on Microelectronic Test Structures.

[30]  Kurt Keutzer,et al.  Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  Tomohiro Kubo,et al.  Suppression of Poly-Gate-Induced Fluctuations in Carrier Profiles of Sub-50nm MOSFETs , 2006, 2006 International Electron Devices Meeting.

[32]  Costas J. Spanos,et al.  Fundamentals of Semiconductor Manufacturing and Process Control: May/Fundamentals of Semiconductor Manufacturing and Process Control , 2006 .

[33]  K. Rochereau,et al.  From MOSFET Matching Test Structures to Matching Data Utilization: Not an Ordinary Task , 2007, 2007 IEEE International Conference on Microelectronic Test Structures.

[34]  Lars Liebmann,et al.  TCAD development for lithography resolution enhancement , 2001, IBM J. Res. Dev..

[35]  J. Johnson,et al.  Lateral ion implant straggle and mask proximity effect , 2003 .

[36]  Dinesh K. Sharma,et al.  Resolution enhancement techniques for optical lithography , 2002 .

[37]  Marcel J. M. Pelgrom,et al.  Transistor matching in analog CMOS applications , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[38]  G. Bouche,et al.  Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance , 2002, Digest. International Electron Devices Meeting,.

[39]  P. Stolk,et al.  Modeling statistical dopant fluctuations in MOS transistors , 1998 .

[40]  Colin C. McAndrew,et al.  Statistical modeling for circuit simulation , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[41]  Youngmin Kim,et al.  Trench isolation step-induced (TRISI) narrow width effect on MOSFET , 2002, IEEE Electron Device Letters.

[42]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[43]  Costas J. Spanos,et al.  Modeling within-die spatial correlation effects for process-design co-optimization , 2005, Sixth international symposium on quality electronic design (isqed'05).

[44]  Oscar Noordman,et al.  Etch, reticle, and track CD fingerprint corrections with local dose compensation , 2005, SPIE Advanced Lithography.

[45]  Glen Kramer,et al.  Application-specific worst case corners using response surfaces and statistical models , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[46]  C. Laviron,et al.  0.248/spl mu/m/sup 2/ and 0.334/spl mu/m/sup 2/ conventional bulk 6T-SRAM bit-cells for 45nm node low cost - general purpose applications , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[47]  R. Ranica,et al.  A Cost-Effective Low Power Platform for the 45-nm Technology Node , 2006, 2006 International Electron Devices Meeting.

[48]  F. Nouri,et al.  NMOS drive current reduction caused by transistor layout and trench isolation induced stress , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[49]  Andrzej J. Strojwas,et al.  Generalization of the photo process window and its application to OPC test pattern design , 2003, SPIE Advanced Lithography.

[50]  B.J. Lin.  Lithography for manufacturing of sub-65nm nodes and beyond , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[51]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2006, 2007 IEEE International Electron Devices Meeting.

[52]  Andrew R. Brown,et al.  Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , 2003 .

[53]  Peter Feldmann,et al.  Statistical integrated circuit design , 1993 .

[54]  R. Lefferts,et al.  An integrated test chip for the complete characterization and monitoring of a 0.25/spl mu/m CMOS technology that fits into five scribe line structures 150/spl mu/m by 5000/spl mu/m , 2003, International Conference on Microelectronic Test Structures, 2003..

[55]  Linda S. Milor,et al.  Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[56]  Koji Nii,et al.  A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[57]  U. Schaper,et al.  Parameter variation on chip-level , 2005, Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005..

[58]  E.J. Nowak,et al.  Modeling of Variation in Submicrometer CMOS ULSI Technologies , 2006, IEEE Transactions on Electron Devices.